The present invention relates to a semiconductor device, and more particularly to an input circuit of a semiconductor device that ensures a stable operation.
A semiconductor device generally includes a signal transferring unit receiving and transferring a signal and a signal processing unit processing the signal transferred by the signal transferring unit according to a unique predetermined operation.
The signal processing unit is generally referred to as a core circuit of a semiconductor device, and as many devices as are allowed by semiconductor device design and processing technology are integrated in the core circuit.
The signal transferring unit includes an input circuit, which transfers an external signal to the signal processing unit within a semiconductor device, and an output circuit, which outputs data transferred from the signal processing unit to the outside.
In a semiconductor device, particularly in a semiconductor memory device, the input circuit primarily receives an external address signal or an external data signal and transfers it to an internal memory core region and the output buffer outputs a data signal corresponding to the inputted address to the outside.
The operation of a semiconductor device is only reliable when accurate buffering is ensured, and therefore the input circuit, which transfers the external data signal or the external address signal to the inside, that performs an accurate buffering operation is desired.
FIG. 1 is a circuit diagram showing an input circuit of a semiconductor device according to a related art, and illustrates an input circuit having a differential amplifier structure in a general semiconductor memory device, for example a DRAM.
The circuit in FIG. 1 includes an input buffer 100 receiving input signals in and inb, a delaying circuit 200 delaying the output signal of the input buffer 100, a clock buffer 300 receiving clock signals CLK, and CLKB and a strobe & latch circuit 400 receiving both the output of the delaying circuit 200 and the output signal of the clock buffer 300.
In general, the input buffer 100 receives and differentially amplifies the input signals in and inb. For example, the control signals in and inb can be an external signal such as a memory address signal, a control signal, or other such signal.
The delaying circuit 200 adjusts a timing, i.e., a setup time or a hold time, that synchronizes the input signals in and inb (e.g., an address signal, a control signal, or other such signal) with a clock.
The clock buffer 300 receives the system clock signals CLK and CLKB from the outside.
The strobe & latch circuit 400 receives both the output of the clock buffer 300 and the output of the delaying circuit 200 and performs a clock synchronization.
The input circuit in FIG. 1 is configured as a differential input buffer that receives a differential signal. Herein, the differential input refers to signals having opposite phases, such as clocks CLK and CLKB.
The input signals in and inb are inputted into the input buffer 100, which differentially amplifies the input signals in and inb. The crossing point of the differential input (the point at which the signal in and the signal inb are crossed) is referred to as VIX.
Herein, generally the level of the crossing point VIX is a voltage reference level Vref, i.e. VCC/2. However, it may also be possible that the level of the crossing point VIX is not exactly adjusted to the level of the reference voltage Vref because of the influence of a noise or other such disturbance in the system.
It is required that an output signal react at a constant speed with respect to the input signal even when the level of the crossing point VIX is higher or lower than the Vref level. Particularly, problems arise when the input potential is low, which results in a delay of the output signal. The delay of the output signal causes large variation in both the setup time and the hold time, and therefore the input circuit does not operate stably.
FIG. 2 is a graph illustrating the variation in the operation speed of the input buffer 100 according to the variation in the input potentials of the input signals in and inb of FIG. 1, and variation in delay extent ‘t’ according to the variation in the input potentials of the input signals in and inb is shown. Herein, ‘t’ is a time taken for the input signals in and inb to be both inputted into the input buffer 100 and then outputted from the input buffer 100. Meanwhile, variation pattern or variation amount of ‘t’ may be varied as the type of the input buffer 100.
FIG. 3 shows a general circuit diagram of a conventional differential amplifying structure, and shows an example of an input buffer 100 having the properties described above with reference to FIG. 2.
In the conventional differential amplifying structure shown in FIG. 3, when an enable signal en becomes a logic high level, a driving transistor 32 is turned on and the input buffer 100 operates. That is, the input buffer 100 compares and amplifies the levels of the input signals in and inb, and outputs a buffer output signal buf_out.
When the enable signal en becomes a logic low level, the driving transistor 32 is turned off and the input buffer 100 no longer operates. That is, when the enable signal en is at a logic low level, the input buffer 100 does not compare the input signals in and inb, rather the input buffer 100 outputs the buffer output signal buf_out at a high level according to the operation of PMOS transistors 34 and 36, which receive the enable signal en through respective gates. The buffer output signal buf_out is maintained at a high level to prevent a node outputting the buffer output signal buf_out from being floated when the input buffer 100 is in the disabled state.
Referring again to FIG. 2, the crossing point VIX is higher than the reference voltage level during the period A PERIOD and the crossing point VIX is lower than the Vref level during the period B PERIOD. FIG. 2 shows that during the period B PERIOD ‘t’ has greater value than during the period A PERIOD. As shown in FIG. 2, as the input levels of the input signals in and inb are decreased, the setup time and the hold time are largely varied by delay of the output signal and thus the input buffer does not operate stably.
As described above, in a related art, voltage differences Vgs between gate and source of NMOS transistors N0 and N1 in FIG. 3 are lower than a threshold voltage Vth when the level of the input voltage of the input buffer is lowered. Therefore, the NMOS transistors N0 and N1 are turned off for a period and the input buffer does not operate normally during this period. As such, there is a problem with the conventional semiconductor device in that a semiconductor memory device may malfunction when the NMOS transistors N0 and N1 are turned off.